The present invention relates to the control of magnetic storage systems for digital computers, and particularly, to discrete time circuitry integrated into a sampled amplitude read channel for synchronous detection of user data and embedded servo data.
This application is related to several U.S. patents, namely U.S. Pat. No. 5,424,881 entitled xe2x80x9cSynchronous Read Channel,xe2x80x9d U.S. Pat. No. 5,359,631 entitled xe2x80x9cTiming Recovery Circuit for Synchronous Waveform Sampling,xe2x80x9d U.S. Pat. No. 5,291,499 entitled xe2x80x9cMethod and Apparatus for Reduced-Complexity Viterbi-Type Sequence Detectors,xe2x80x9d U.S. Pat. No. 5,297,184 entitled xe2x80x9cGain Control Circuit for Synchronous Waveform Sampling,xe2x80x9d and U.S. Pat. No. 5,329,554 entitled xe2x80x9cDigital Pulse Detector.xe2x80x9d All of the above-named patents are assigned to the same entity, and all are incorporated herein by reference.
In magnetic disk storage systems for computers, digital data serves to modulate the current in a read/write head coil so that a sequence of corresponding magnetic flux transitions are written onto a magnetic medium in concentric tracks. To read this recorded data, the read/write head passes over the magnetic medium and transduces the magnetic transitions into pulses in an analog signal that alternate in polarity. These pulses are then decoded by read channel circuitry to reproduce the digital data.
Decoding the pulses into a digital sequence can be performed by a simple peak detector in a conventional analog read channel or, as in more recent designs, by a discrete time sequence detector in a sampled amplitude read channel. Discrete time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interference (ISI) and, are less susceptible to noise. As a result, discrete time sequence detectors increase the capacity and reliability of the storage system.
There are several well known discrete time sequence detection methods including discrete time pulse detection (DPD), partial response (PR) with Viterbi detection, maximum likelihood sequence detection (MLSD), decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTS/DF).
In conventional peak detection schemes, analog circuitry, responsive to threshold crossing or derivative information, detects peaks in the continuous time analog signal generated by the read head. The analog read signal is xe2x80x9csegmentedxe2x80x9d into bit cell periods and interpreted during these segments of time. The presence of a peak during the bit cell period is detected as a xe2x80x9c1xe2x80x9d bit, whereas the absence of a peak is detected as a xe2x80x9c0xe2x80x9d bit. The most common errors in detection occur when the bit cells are not correctly aligned with the analog pulse data. Timing recovery, then, adjusts the bit cell periods so that the peaks occur in the center of the bit cells on average in order to minimize detection errors. Since timing information is derived only when peaks are detected, the input data stream is normally run length limited (RLL) to limit the number of consecutive xe2x80x9c0xe2x80x9d bits.
As the pulses are packed closer together on the concentric data tracks in the effort to increase data density, detection errors can also occur due to intersymbol interference, a distortion in the read signal caused by closely spaced overlapping pulses. This interference can cause a peak to shift out of its bit cell, or its magnitude to decrease, resulting in a detection error. The ISI effect is reduced by decreasing the data density or by employing an encoding scheme to ensure that a minimum number of xe2x80x9c0xe2x80x9d bits occur between xe2x80x9c1xe2x80x9d bits. For example, a (d,k) run length limited (RLL) code constrains to d the minimum number of xe2x80x9c0xe2x80x9d bits between xe2x80x9c1xe2x80x9d bits, and to k the maximum number of consecutive xe2x80x9c0xe2x80x9d bits. A typical RLL code is a (1,7) ⅔ rate code which encodes 8 bit data words into 12 bit codewords to satisfy the (1,7) constraint.
Sampled amplitude detection, such as partial response (PR) with Viterbi detection, allows for increased data density by compensating for intersymbol interference and increasing channel noise immunity. Unlike conventional peak detection systems, sampled amplitude recording detects digital data by interpreting, at discrete time instances, the actual value of the pulse data. The analog pulses are sampled at the baud rate (code bit rate) and the digital data is detected from these discrete time sample values. A discrete time sequence detector, such as a Viterbi detector, interprets the discrete time sample values in context to determine a most likely sequence for the data. In this manner, the effect of ISI can be taken into account during the detection process, thereby decreasing the probability of a detection error. This increases the effective signal to noise ratio and, for a given (d,k) constraint, allows for significantly higher data density as compared to conventional analog peak detection read channels.
The application of sampled amplitude techniques to digital communication channels is well documented. See Y. Kabal and S. Pasupathy, xe2x80x9cPartial Response Signalingxe2x80x9d, IEEE Trans. Commun. Tech., Vol. COM-23, pp.921-934, September 1975; and Edward A. Lee and David G. Messerschmitt, xe2x80x9cDigital Communicationxe2x80x9d, Kluwer Academic Publishers, Boston, 1990; and G. D. Forney, Jr., xe2x80x9cThe Viterbi Algorithmxe2x80x9d, Proc. IEEE, Vol. 61, pp. 268-278, March 1973.
Applying sampled amplitude techniques to magnetic storage systems is also well documented. See Roy D. Cideciyan, Francois Dolivo, Walter Hirt, and Wolfgang Schott, xe2x80x9cA PRML System for Digital Magnetic Recordingxe2x80x9d, IEEE Journal on Selected Areas in Communications, Vol. 10 No. 1, January 1992, pp.38-56; and Wood et al, xe2x80x9cViterbi Detection of Class IV Partial Response on a Magnetic Recording Channelxe2x80x9d, IEEE Trans. Commun., Vol. Com-34, No. 5, pp. 454-461, May 1986; and Coker Et al, xe2x80x9cImplementation of PRML in a Rigid Disk Drivexe2x80x9d, IEEE Trans. on Magnetics, Vol. 27, No. 6, November 1991; and Carley et al, xe2x80x9cAdaptive Continous-Time Equalization Followed By FDTS/DF Sequence Detectionxe2x80x9d, Digest of The Magnetic Recording Conference, Aug. 15-17, 1994, pp. C3; and Moon et al, xe2x80x9cConstrained-Complexity Equalizer Design for Fixed Delay Tree Search with Decision Feedbackxe2x80x9d, IEEE Trans. on Magnetics, Vol. 30, No. 5, September 1994; and Abbott et al, xe2x80x9cTiming Recovery For Adaptive Decision Feedback Equalization of The Magnetic Storage Channelxe2x80x9d, Globecom""90 IEEE Global Telecommunications Conference 1990, San Diego, Calif., November 1990, pp.1794-1799; and Abbott et al, xe2x80x9cPerformance of Digital Magnetic Recording with Equalization and Offtrack Interferencexe2x80x9d, IEEE Transactions on Magnetics, Vol. 27, No. 1, January 1991; and Cioffi et al, xe2x80x9cAdaptive Equalization in Magnetic-Disk Storage Channelsxe2x80x9d, IEEE Communication Magazine, February 1990; and Roger Wood, xe2x80x9cEnhanced Decision Feedback Equalizationxe2x80x9d, Intermag""90.
Similar to conventional peak detection systems, sampled amplitude detection requires timing recovery in order to correctly extract the digital sequence. Rather than process the continuous signal to align peaks to the center of bit cell periods, as in peak detection systems, sampled amplitude systems synchronize the sampling of the pulses to the baud rate. That is, timing recovery adjusts the sampling clock in order to minimize the error between the signal sample values and estimated sample values. A pulse detector or slicer determines the estimated sample values from the read signal samples. Even in the presence of ISI the sample values can be estimated and, together with the signal sample values, used to synchronize the sampling of the analog pulses in a decision-directed feedback system.
The decision-directed feedback system is normally implemented using a phase-locked-loop (PLL) circuit comprising a phase detector for generating a phase error based on the difference between the estimated samples and the read signal samples. A loop filter filters the phase error, and the filtered phase error operates to adjust the sampling clock which is typically the output of a variable frequency oscillator (VFO) with the filtered phase error as the control input. The output of the VFO controls the sampling clock of a sampling device such as an analog-to-digital (A/D) converter.
It is helpful to first lock the PLL to a reference or nominal sampling frequency so that the desired sampling frequency, with respect to the analog pulses representing the digital data, can be acquired and tracked more efficiently. The nominal sampling frequency is the baud rate, the rate that data was written onto the medium. Therefore, one method to lock-to-reference is to generate a sinusoidal signal relative to the write clock and inject this signal into the PLL. Once locked to the reference frequency (write frequency), the PLL input switches from the write clock to the signal from the read head in order to synchronize the sampling of the waveform in response to a sinusoidal acquisition preamble recorded on the medium.
The timing recovery loop filter controls the dynamics of the phase-lock-loop. Accordingly, the loop filter coefficients are adjusted to achieve a desired transient response and tracking quality. For good tracking quality, the loop bandwidth should be narrow so that phase noise and gain variance are attenuated. During acquisition, the loop bandwidth should be as wide as possible without being unstable to achieve a fast transient response in order to minimize the length of the acquisition preamble.
Sampled amplitude read channels also employ a decision-directed feedback system to control the gain of the analog read signal in order to minimize a gain error between the signal sample values and estimated sample values. The gain error is filtered and applied to the control input of a variable gain amplifier (VGA) in order to adjust the magnitude of the read signal toward the desired partial response.
A DC offset in the analog read signal can adversely affect the performance of the automatic gain control and timing recovery circuitry. A decimation DC offset circuit can compensate for the undesirable effects by computing the DC offset from the read signal sample values and subtracting it from the analog read signal before sampling (see, e.g., the above referenced co-pending U.S. patent application Ser. No. 08/341,251). Similar to the gain control and timing recovery loops, the DC offset loop comprises a filter for filtering the computed DC offset.
Also relevant to the present invention is the servo control system for positioning the read/write head over a selected track in order to read and write information. In disk drives utilizing either analog or sampled amplitude read channels, the read/write head is normally mounted on an actuator arm which is positioned by means of a voice coil motor (VCM). The VCM moves the head and actuator arm assembly across the disk surface at a very high speed to perform seek operations in which the head is positioned over a selected data track. The VCM also maintains the head over the selected track while reading or writing information as successive portions of the track pass under the head. A servo system controller provides the head positioning necessary for reading and writing information in response to requests from a computer to which the disk drive is connected.
In embedded servo disk drives, servo fields are normally recorded on the disk as radial spokes 17 that xe2x80x9csplitxe2x80x9d the data sectors 15 as shown in FIG. 2A. Each servo spoke 17 is referred to as a xe2x80x9cwedgexe2x80x9d of servo data comprising servo control information and servo data. The servo control information typically includes a preamble 5 to allow gain control to acquire to the read signal before reading the servo data, and a servo synch mark 7 to signal the beginning of the servo data 3 (see FIG. 2B). If the servo data is detected synchronously, then the preamble is also used to synchronize timing recovery to the read signal before reading the servo data. The servo data may also comprise a track number code which is a Gray coded integer value of the track currently spanned by the read/write head, a head number identifying the current platter in a multi-disk system, and a wedge number identifying the current servo wedge. The servo data may also optionally comprise a servo address mark for asynchronous identification of the wedge when the disk drive spins up initially.
The embedded servo field also typically includes off-track burst information physically positioned at precise intervals and locations with respect to the various track centerlines to provide the servo system controller with information relative to the fractional track-to-track displacement of the head with respect to a selected track centerline. The servo controller uses the servo burst information to keep the read head aligned over the centerline of the selected track while data is written or read from the medium.
Similar to the servo data sectors, the user data sectors 15 also comprise an acquisition preamble 68 and a sync mark 70 to signal the beginning of a user data field 72 as shown in FIG. 2B.
Zoned recording is a technique known in the art for increasing the storage density by recording the user data at different rates in predefined zones between the inner diameter (ID) and outer diameter (OD) tracks. The data rate can be increased at the outer diameter tracks due to the increase in circumferential recording area and the decrease in intersymbol interference. This allows more data to be stored in the outer diameter tracks as is illustrated in FIG. 2A where the disk is partitioned into an outer zone 11 comprising fourteen data sectors per track, and an inner zone 13 comprising seven data sectors per track. In practice, the disk may actually be partitioned into several zones at varying data rates.
When using synchronous detection to read the servo fields, the read channel operates in the same manner as if it were reading user data as described above. That is, the gain and DC offset circuitry adjust the amplitude and offset of the analog read signal, and timing recovery locks to a reference frequency, acquires the servo preamble, and synchronizes the sampling of the servo data. In most disk drive storage systems, however, the embedded servo fields are not recorded at the same rate as the user data. There is, therefore, a deficiency in the operation of read channels that cannot re-program the gain control, timing recovery, and DC offset circuits when the read channel transitions between reading user data and servo data.
Other drawbacks overcome by the present invention include: the inability to pipeline reads to reduce the gap between sectors; the inability to use the read channel sampling device for sampling other analog signals generated by the storage system such as servo control signals; the inability to use information provided in the preamble field to optimize operation of the sync mark detector; the inability to detect the user data sync mark and the servo data sync mark using the same sync mark detector; and the inability to adjust the response of the gain control loop when searching for the servo address mark.
What is needed is a robust technique for re-programming the gain control, DC offset control, and timing recovery control circuits when the read channel transitions between reading user data and embedded servo data. Another object is to pipeline reads to minimize the gap on the medium between adjacent user data sectors and the gap between user data and servo data sectors. A further object is to use the read channel sampling device for sampling auxiliary analog signals generated by the storage system. Another object is to use the same sync mark detector for detecting the user data sync mark and the servo data sync mark. Yet another object is to enable operation of a sync mark detector at a clock interval selected in relation to the preamble. A further object is to adjust the frequency response of the gain control loop when searching for the servo address mark.
In a sampled amplitude read channel for reading user data and embedded servo data in a magnetic disk storage device, a plurality of components including a timing recovery circuit, an automatic gain control circuit, and a DC offset circuit comprise at least one filter programmed from a set of xe2x80x9cshadowxe2x80x9d registers corresponding to whether the read channel is in a user data or servo data mode. The filter coefficients and accumulation paths are updated from the shadow registers when the read channel transitions between reading user data and embedded servo data. The magnetic disk is partitioned into several zones, and the filters are initialized with calibrated values when the read/write head passes into a new zone.
The timing recovery circuit comprises a phase-locked-loop for synchronizing the sampling of an analog read signal generated from the read head passing over the magnetic medium. The timing recovery PLL includes a variable frequency oscillator (VFO) comprising an output for controlling the sampling frequency of a sampling device; a first control input for receiving a channel data rate (CDR) command; and a second control input for receiving a center frequency command. The CDR command is programmably set from a user/servo shadow register according to the zone where the selected track is located.
The PLL center frequency command comprises a course setting, a bias setting and a fine setting. The course setting is generated either by a user data synthesizer or a servo data synthesizer depending on the user/servo mode of the read channel. The bias setting is programmably set from a user/servo shadow register and compensates for differences in fabrication between the synthesizer VFOs and the timing recovery VFO. The fine setting is generated by a discrete time phase error detector which measures a difference between the sampling phase/frequency and the baud rate.
Before acquiring the acquisition preamble preceding the user or servo data, the timing recovery PLL is locked to the output of the user or servo synthesizer depending on the user/servo mode. This is accomplished by injecting, into the read channel, the analog output signal from the respective synthesizer so that timing recovery locks onto the appropriate frequency.
In order to reduce the gap between adjacent user data sectors and the gap between user data and servo data sectors, operation of the read channel is pipelined by resetting the gain, timing recovery, and DC offset circuits before the discrete time equalizing filter and sequence detector have finished processing the samples for the current sector. This allows the read channel to begin acquiring the preamble of a next sector (user or servo data) concurrent with processing the end of the previous sector, thereby decreasing the physical gap on the medium between sectors.
The read channel also comprises a programmable sync mark detector for detecting both the user data and servo data sync marks in order to frame the operation of respective RLL user data and servo data decoders. The sync mark detector is enabled by the timing recovery circuit at a sample interval predetermined in relation to the preamble field.
When the disk drive initially spins up, an asynchronous servo address mark detector determines the location of the servo wedges with respect to the read head. To facilitate asynchronous detection, the gain control circuit computes a gain error according to a predetermined set point and the maximum absolute value over a programmable block length.